1. Field of the Invention
The present invention relates to the field of digital electronic systems. More particularly, the present invention relates to the field of buffer circuits used for the communication of information between two or more digital domains.
2. Related Art
Digital computer systems today often are interfaced together with multiple different and or separate domains. Networked computer systems often employ adapters, routers and switches that require data queuing for various reasons. The different or separate digital domains can have address/data/control buses that operate according to different communication protocols and/or operate at different data transfer rates. For instance, a computer system can have one digital domain operating in accordance with the PCI (Peripheral Component Interconnect) bus protocol and another digital domain operating in accordance with the ISA (Industry Standard Architecture) bus protocol. When interfacing digital domains having different bus protocols and/or having different data transfer rates, it is common to employ a buffer circuit located physically in between the digital domains to facilitate information communication between the two domains. The buffer acts to queue data in order to prevent any data loss due to the different data transfer rates and/or communication protocols.
Further, even between digital domains of the same data transfer rate and/or of the same communication protocol, it is common to employ buffer circuits between the domains to facilitate bursting operations between one or more of the domains. In this capacity, the buffer circuit also acts as a data queue. Data bursting is often done for improving the communication rate between domains and/or for handling prefetching operations, etc. For instance, a PCI target device which pipes data from the PCI bus to a memory unit (e.g., a random access memory, RAM) requires a data queue because the PCI bus can burst data in consecutive cycles while the RAM might take two cycles, or more, to complete one transaction. In these cases, the buffer circuit acts as a temporary holding place for the bursted data until the other domain can accept, e.g., read, the data.
In the past, first-in-first-out (FIFO) buffer circuits of the design 10, as shown in FIG. 1A, have been used to provide the data queuing functionality as described above. Prior art FIFO buffer circuit 10 includes i number of multi-bit register stages 12a-12i which are clocked by common clock 20. Only one bit of each register stage is shown in FIG. 1A for clarity. Data is received from a first domain/device at port 14 and stored in cell 12i (e.g., the upstream most cell) and is output to a second domain/device at port 16. As each new data is received at 12i, the existing data of FIFO buffer 10 is shifted by one register to the right, e.g., toward the output port 16. The problem with prior art FIFO buffer circuit 10 is that each new data must be received by the upstream most register 12i at port 14 and must traverse through all i stages until it is allowed to exit at port 16 (e.g., first-in-first-out). This is true even if FIFO buffer 10 is completely empty when the first of the new data is received. Therefore, there exists an i cycle latency (minimum) for each data received by the prior art FIFO buffer 10 regardless of its prior or current state of vacancy. Moreover, with respect to scaleability, the more register stages that are added to FIFO buffer circuit 10, the larger its minimum latency becomes. Therefore, it would be advantageous to provide a buffer design that does not have such a large latency as is characteristic of the FIFO buffer circuit 10. It would be advantageous further to provide a buffer design having a latency that does not necessarily increase with an increase in its storage capacity.
A second prior art buffer design 30 is shown in FIG. 1B that utilizes a dual ported random access memory (RAM) unit 42 as the data queue device. In buffer design 30, the first domain communicates over bus 32 with a first interface circuit 40a which is coupled to dual port RAM 42. Dual ported RAM 42 is coupled to interface 40b which communicates to the second domain over bus 36. Buffer design 30 does not have latency problems to the extent of buffer design 10 (FIG. 1A). However, the problem with buffer design 30 is that it is very complex to design and implement. For instance, the interface circuits 40a-40b require complex controller circuits, complex finite state machine designs, and complex counter and pointer logic to implement. Moreover, once designed, the interface circuits 40a-40b are generally specific to the size of the memory 42 and are not readily scaleable in size. For instance, if the memory 42 needs to be increased or decreased, then the interface circuits 40a-40b need to be redesigned. Therefore, it would be advantageous to provide a buffer design that does not require complex interface circuitry. It would also be advantageous to provide a buffer design whose interface circuitry is readily adaptable to changes in the capacity of the buffer.
Accordingly, the present invention provides a buffer design that does not have such a large latency as is characteristic of the FIFO buffer 10. The present invention further provides a buffer design having a latency that does not necessarily increase with an increase in storage capacity of the buffer. Moreover, the present invention provides a buffer design that does not require complex interface circuitry. The present invention also provides a buffer design whose interface circuitry is readily adaptable to changes in the capacity of the buffer. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.